1. Field of the Invention
The present invention is generally in the field of testing integrated circuits and modules. More specifically, the present invention is in the field of at-speed testing of integrated circuits and modules.
2. Background Art
As chip designs continue to decrease in size and increase in complexity, it has become more difficult to effectively test defects in the functional logic of a chip. Accurate, inexpensive, and easy to implement testing methods are necessary to ensure that defective chips are not shipped to customers.
In a conventional regular scan test, an automatic test equipment (“ATE”) or another testing equipment (such as those used in lab testing or “bench testing”)—collectively referred to as a “tester” (or “testers”) in the present application—provides a test clock and test data to test the various permutations of the functional logic of the integrated circuit. However, testers are expensive and require a considerable amount of time to thoroughly test the functional logic of the integrated circuit, and have become increasingly inadequate and inaccurate in today's high-speed integrated circuits. Another conventional method, called an “at-speed” test, can test an integrated circuit at the operational frequency of the integrated circuit. However, most testers are incapable of supplying accurate “at-speed” clock and data signals to the integrated circuit and/or detecting and measuring “at-speed” signals from the integrated circuit at these high operating speeds.
To avoid the difficulties and expense of testing the functional logic of integrated circuits with off-chip testers, another conventional method uses an on-chip design. This conventional method modifies a phase-locked loop (PLL) clock to generate a test clock with only two pulses, a launch pulse and a capture pulse. The launch pulse is applied to an integrated circuit, and the capture pulse is used to capture or read the output of the integrated circuit after data has propagated through the integrated circuit's functional logic. However, because this method is limited to producing two consecutive clock pulses (i.e., launch and capture pulses), it is unable to test integrated circuits where data takes longer than one clock pulse to propagate through the functional logic.